Modern processors (e.g., microprocessors) typically include several binary adder circuits (i.e., “adders”). For example, one adder is typically used in an integer arithmetic logic unit (ALU) for performing addition, subtraction, multiplication, and division. A floating-point processor may include two adders: one for processing the mantissa, and another for processing the exponents. Additional adders may be used to compute relative addresses for memory access and branch instructions.
In many processor designs, the speed of the processor is limited by the time required to perform an addition operation in the ALU. In general, binary adders are performance-critical components of modern processors. Further, as processor clock signal frequencies increase and periods decrease, implementing “wide” adders (e.g., 64-bit adders) capable of producing sums and carry signals during single cycles of processor clock signals becomes increasingly difficult.
Although adders implemented in dynamic logic may compute sums and carry signals faster than static logic implementations, static logic implementations are still desirable due to the typical higher power consumption and the increased susceptibility to noise of dynamic logic circuits.
The multiplicity of “fast” static adder designs includes carry look ahead adders and carry select adders. In a typical carry look ahead adder, an addend A and an augend B are divided into multiple sections or “blocks” AI and BI. In general, bits within each block, and a carry from a previous block (e.g., a carry in), are added to form a sum and a carry out for the block. Generate signals GI and propagate signals PI are computed for each block, and logically combined to compute the carry out:    PI=AI+BI where ‘+’ represents logical OR (or alternately PI=AI XOR BI)    GI=AI·BI where ‘·’ represents logical AND    Carry In=CI+1 (where lower numbered bits are more significant)    Carry Out=CI=GI+PI·CI+1 (where lower numbered bits are more significant)    Sum=AI XOR BI XOR CI (or Sum=PI XOR CI where PI=AI XOR BI)The carry look ahead technique saves time by allowing carry signal computations to be overlapped (i.e., by allowing the carry signals to be computed substantially in parallel).
Carry select adders are also popular choices due to their relatively small gate fanouts (numbers of gate inputs driven by each gate output) and relatively small numbers of gate stages compared with other static adder implementations (e.g., carry look ahead adders). In a typical carry select adder, as in the typical carry look ahead adder, an addend A and an augend B are divided into multiple sections or blocks. In general, bits within each block, and a carry from a previous block (e.g., a carry in), are added to form a sum and a carry out for the block.
Unlike the carry look ahead adder, the carry select adder performs two separate addition operations for each block: one with a carry in (i.e., an assumed carry in) of ‘0’, and the other with a carry in (i.e., an assumed carry in) of ‘1’. The results of the two addition operations are called “presums” and are typically provided to inputs of a multiplexer. The carry out produced by the previous block is used to control the multiplexer such that the multiplexer selects the correct presum. The carry out produced by the previous block also determines the carry out produced by the current block. The carry select technique saves time by computing all possible presums, then selecting from among the presums dependent upon the actual carry signals.
As processor clock signal frequencies continue to increase, a continuing need exists for adders capable of producing sums and carry signals in shorter periods of time.